1. Field of the Invention
The invention relates to optimize source/drain and gate with low resistance, more particularly by using silicide technology to optimize performance of source/drain and gate.
2. Description of the Prior Art
As the time being, integration of integrated circuit, semiconductor device is gradually increased greatly than before. Size of semiconductor device is shorter and shorter than before as well. Therefore, it is important that keeping good operation condition even though the size of semiconductor is measured as small as angstroms. Particularly preferring conventional complementary metal-oxide semiconductor (C.M.O.S.) device, usually used as high-voltage device, is seriously mentioned. Generally the conventional horizontal-direction C.M.O.S. structure will occupy much of space of chip due to it is a widely deposition device. Also, the channel and drift area of conventional C.M.O.S. will occupy horizontal-direction space of chip. Therefore, if possible, it is necessary to be modified geometry of C.M.O.S. device.
Secondly, as the C.M.O.S. channel becomes shorter, the electric field along the channel becomes stronger (for a given power supply voltage). That is, the potential distribution becomes two dimensional, and the effect of the electric field along the channel can no longer be ignored while considering the effects of the electric field normal to the channel.
The conventional art is shown as FIG. 1A to FIG. 1E. From the cross sectional diagram of FIG. 1A, substrate 10, shallow trench isolation 11, N-well and P-well 12 are all provided.
Then, as FIG. 1B, gate oxide 13 is grown up and polysilicon gate 14 is formed by the conventional deposition.
Sequentially, LDD implants can be carried out as source/drain region 15 as FIG. 1C.
For spacer 16 formation, it is shown as FIG. 1D. Again, referring with FIG. 1D, N+ and P+ well region 15 all will be formed by implanting. Next, source/drain are all annealed as indicated FIG. 1D.
Finally, FIG. 1E shows that sacilide 17 can be formed at the same time on source/drain region 15 and on top surface of polysilicon gate 14.
As semiconductor device is gradually scaled down, for lower junction leakage of ultra-shallow junction source/drain, thickness in silicide should be reduced. Thus, the scale of silicide on polysilicon gate is also reduced. This will make sheet resistance increase very much in the practical. Therefore, the above problem should be involved in the semiconductor process. It is necessary to widely employ the silicide process for the ultra large semiconductor integrated (ULSI) process.